FinFET structure
As posted earlier, semiconductor industry attempts to improve the chip on the basis of power, area, cost, speed of operation and time to market. In fact, Moore’s law is all about optimising those parameters by driving to the smallest possible transistor size with each new technology generation. Even though transistor size has been decreasing , recently certain parameters like power-supply voltage are not achieving similar scaling. Furthermore, optimising one parameter might exacerbate other parameters and ultimately the whole design.
In case of planar transistor technology, as we scale, the effect of leakage current due to Continue reading →