Researchers at Stanford University and MIT have built a new chip using carbon nanotube field-effect transistors and resistive random access memory (RRAM) . These two things are built vertically over one another, giving rise to new 3-D computer architecture with interleaving layer of logic and memory. The layers are connected by ultra dense wires to address the issue of communication bottleneck, which is often encountered when two different chips communicate. The 3D chip is able to store massive amount of data and perform computation on them, without getting limited by interconnects within and between chips.
In addition to that, researchers used carbon nanotubes as sensors and placed over 1 million carbon nanotube based sensors on the top layer, which is used to detect and classify ambient gases. Due to the layers of sensing, storage and computation, the chip was able to measure each of the sensors in parallel and write directly to memory.
According to Jan Rabaey (professor of electrical engineering and computer science at University of California, Berkeley), three-dimensional integration is the most promising approach to continue the technology scaling path set by Moore’s law.
Read this article from MIT News to know more.
The Future Chip 